Diode Projects

BMS for EV

BMS for EV

Lithium batteries provide excellent energy storage capabilities at a relatively high density. The downside is we need to monitor these cells to ensure safe operation to increase their lifespan. For this purpose, we need a battery management system that optimizes cell performance by continuously monitoring the cell parameters. The BMS limits the cell voltage, current, and temperature and ensures cell balancing keeping these parameters in safe operating conditions. We are designing a BMS for 18650 Li-ion battery packs of 24 cells in a 4s6p configuration.
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Brain Image Analysis

Brain Image Analysis

Leveraging image processing and machine learning algorithms to diagnose brain diseases
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Crypto Prediction Exchange App

Crypto Prediction Exchange App

Prediction of cryptocurrency prices based on past data in the form of a react-based app
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Segmentation of Medical Images

Segmentation of Medical Images

Medical image segmentation has an essential role in computer-aided diagnosis systems in different applications.Image segmentation is the procedure of dividing a digital image into a multiple set of pixels. The prior goal of the segmentation is to make things simpler and transform the representation of medical images into a meaningful subject.
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Quantum Algorithms

Quantum Algorithms

Module that aims at allowing basic quantum algorithms to be solved using one line of code only. The first version integrates the following algorithms: Bernstein-Vazarani (berVaz), Deutsch–Jozsa (deuJoz), Grover Search (groveSearch) and Shor's Factoring Algorithm (shor).
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RDNA2 Based Compute Unit

RDNA2 Based Compute Unit

This project aims to implement the scalar ALU in compliance with RDNA2 ISA. The RDNA2 ISA is found in the commercial GPUs of AMD which comprises of the Radeon RX6000 series of GPUs. The implemented ALU can run all the supported instruction types as documented in the RDNA2 ISA.
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Simulation of a SDR with CR Technique

Simulation of a SDR with CR Technique

Simulation of a basic software defined radio with cognitive radio technique using MALTALB/Simulink
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VLSI Design of RISC Processor

VLSI Design of RISC Processor

This project aims at designing an optimized MIPS Pipelined processor from scratch. The processor includes 5 pipeline stages - Instruction fetch, Decode, Execute, Memory access and Write back. The project involves the behavioural modelling of the processor in Verilog and generate it's physical design using Openlane - an opensource tool used to generate GDS II file from the RTL netlist. The OpenLane physical design tool is also used to select optimized synthesis strategy and to compare the designs obtained with varying the parameters.
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